Optimizing QFN Footprints For Contract Electronics Assembly Provider

The hallmark of any good supply chain services provider is its ability to accommodate a repertoire of specialized engineering expertise such as manufacturing and contract electronics assembly packages. Selecting the wrong EMS (electronic manufacturing service) provider not only escalates production costs, it can also jeopardize your reputation and position in the market.Due to burgeoning competition, it is imperative that the norms of quality and customer satisfaction be adhered to completely. In this context, the emergence of QFN package has been a major boon to innovative and upcoming engineering/manufacturing firms. 

QFN- An Overview

The Quad Flat No-lead (QFN) forms part of the family of new contract electronic assembly packages belonging to the PCB contract electronic product assembly line. Featuring pins on all four edges of its bottom surface, the plastic encapsulated package (CPS) has both symmetric and asymmetric patterns.

The launch of QFN was necessitated by the inability of Quad Flat Package (QFP) to embed leads into the plastic, which resulted in inadequate, unreliable assembly packaging. QFN allows embedded lead form to work well with high speed designs (owing to shorter die to lead bonding time) to produce large quantities of heat.

The QFN is essentially a leadless package that is based on the copper lead frame substrate. It establishes electrical contact with the PCB through adequate lead soldering on its bottom portion. QFN’s unique design leads to improved performance which in many cases raises the 2 GHz frequency to 10 GHz without losing out on efficiency.

Design Particulars

With symmetric pins, it is usually available in 0.4 mm, 0.5 mm, 0.65 mm, 0and .8 mm in accordance to the JEDEC MO-220I standard. The die pad of the QFN and perimeter I/O pads get processed using copper lead substrate. It is subsequently assimilated into the plastic using the die pad and I/O pads which are soldered to the contract electronic assembly package.Here, the expertise of the company becomes vitally critical because it needs to ensure that the soldering not only ensures long term dependability, but also safeguards I/O pad joints.

Solder Masking

The main purpose of the thermal tab is to draw heat away from the die. A great way to do that is to add a set of thermal vias to the buried copper planes. They should be 0.3mm-0.33mm in diameter and can be increased, depending upon the size of the thermal lands.  You need solder masking to prevent solder wicking inside the thermal vias by taking the solder away. Therefore, experts suggest that its diameter must be 100µm bigger than that of the vias, which can subsequently be connected to the mask through the top or bottom. 

Land Patterns

I/O lands must ideally be 0.2mm longer than the I/O pads, although their widths should be same. There are generally two patterns used: NSMD (Non-Solder Mask Defined) and SMD (Solder Mask Defined).  In NSMD, solder openings are tinier than metal pads while the 
opposite is true in case of SMDs.

NSMDs allow greater control of the assembly manufacturing process while lending stability to the solder joints. The solder mask openings are required to be bigger by 120µm to 150µm than the pad size to allow greater efficiency. Unlike NSMDs, SMDs are often unreliable and used only in certain projects.