2017-11-30 18:48:11
viya
107

The DTL or diode transistor logic first became available commercially in 1962. The circuit diagram for a two-input DTL NAND gate is shown in Fig. 9.2(a) and although it is no longer available it does provide a useful introduction to the TTL logic family which follows. Before proceeding we need to point out that when the voltage across a diode equals 0.7 V (anode (A) voltage with respect to cathode K)) then current and this is called forward bias. Any voltage less than will result in negligible current flow. The two conditions are shown on a current/voltage plot in Fig. 9.2(b).

The circuit in Fig. 9.2(a) is actually a two-input AND gate followed by a NOT gate (i.e. a NAND gate) and functions as follows. If one input is low (less than 0.2 V) then the corresponding diode is forward biased and the voltage appearing at point 'P* is 0.9 V (since 0.7 V exists across a forward biased diode).This voltage, however, is insufficient to turn on diodes D3 and D4 and so the voltage appearing at the base of T1 is insufficient to turn on transistor Tl. The current flowing through TI is small and so the voltage dropped across R3 is also small and the output voltage is therefore close to 5 V i.e. a logic 1. Thus when either or both of the inputs are low the output is high.

Now if both inputs are high then the diodes D1 and D2 are turned off and the voltage at point ‘P’ rises to turn on diodes D3 and D4. Hence the voltage appearing at the base of Tl is dictated by the values of resistors R1 and R2. If R1 and R2 are chosen carefully then transistor Tl can be turned on and the output will be or 0.2 V.

So to summarise: if either or both inputs are low the output transistor, Tl, is turned off and hence the output is high; if, however, both inputs are high (‘1’) then the transistor Tl is turned on and the output is low (‘0’). The circuit thus operates as a two-input NAND gate.

To turn on TI we need a base-emitter voltage of 0.7 V. Hence using KVL from to R2 reveals:

Since we know VK then to find R1 we need to know I1, which from Kirchhoff, Current Law (KCL) is equal to the sum of I2 and Ib since D1 and D2 are off. Calculating each of these currents gives:

Therefore /,=0.588mA and substituting this into the above equation for VCC to find R1 gives:

Standard TTL (Transistor Transistor Logic) - 74 series

The standard TTL (short for Transistor Transistor Logic) logic gate was first marketed in 1963 under part numbers 74XXX. For example the 7400 is a quadruple (i.e. it contains four) two-input NAND gate in one package whilst the 74174 is a Hex D-type (i.e. six D-types in one package). The circuit diagram for a single two-input NAND gate implemented in TTL is shown in Fig. 9.3. Although it is not immediately obvious it does build on the DTL design of Fig. 9.2(a). The diodes Dl，D2 and D3 have been replaced by a single transistor (T1) that has a multiemitter (two emitters in this case). The diode EM and resistor R2 is replaced by the R2, T2 and R3 configuration. Finally the output stage has been replaced by a circuit that is called a totem pole3 output. The multiemitter input transistors quite simply an NPN transistor with more than one emitter which mimics the operation of the two diodes D1 and D2. The circuit operates as follows.

If at least one input is low (0.2 V) then that emitter is forward biased and the transistor is turned on (with current flowing out of the input that is low). A voltage of Vcesat (0.2 V) appears across T1 and hence the voltage at the base of T2is 0.4 V (i.e. 0.2+0.2). This is insufficient to turn on transistor T2 and hence the current through R2 and R3 is negligible. Consequently, the voltage at the base of T3 is 0 V and at the base of T4 is approximately 5 V. Hence T4 is turned onbut^1 quite saturated and the output is high - but how high?

TAG: Logic Gate

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