The Totem-Pole Output Stage

2017-12-01 18:16:00 viya 91

At the output of all gates there is a capacitive load (CL) caused by the input capacitance of the next stage. This could be a printed circuit board interconnect or quite simply an oscilloscope lead. With the DTL circuit of Fig. 9.2(a) when the output changes from low to high, this capacitance (C^ has to be charged through the collector resistor R3. Hence the delay time for the output to charge from low to high (i.e. ‘0’ to ‘1’)is limited by the time constant R3 x CL. To reduce this we could just reduce the value of R3 but then the power consumption will increase when the output transistor T1 is on.

The totem-pole output Fig. 9.3 gets around these problems. When the output is charging, the time constant is now dependent upon the resistance of the transistor T4, diode D1 and R4. Since R4 is only 1300 and both T4 and D1 are on then the time constant is much smaller than the DTL output circuit and hence the low-to- high delay is greatly reduced. In this case the transistor T3 is off and power consumption is low. This type of circuit is called an The presence of both DI and R4 are essential for the reliable operation of the TTL output stage. When the output is low, i.e. T3 on, the base of T4 is at a potential of: Vbe3 + Vcesat2 = 0.7+0.2 = 0.9V. Since the output is 0.2V then this is insufficient to turn on the combination of T4 and D1 which results in no current being drawn from the supply. However, without the diode Dl, then T4 will turn on and current will flow into T3 thus consuming power and the output voltage will rise (due to the resistance of T3) to a level between a low’ and a £high’ (i.e. an illegal state). Hence Dl is inserted to keep T4 turned off when T3 is on. Resistor R4 is present so as to limit the current when the output is high and thus provides a short circuit protection if the output is inadvertently tied to 0 V.


Example 9.6                                

Many other logic gates can be implemented with the standard 74 series. What function does the circuit in Fig. 9.4 perform? Assume F1L=0.2 V and KIH=3.6V.

The Totem-Pole Output Stage


A=0.2 V, B=0.2 V. Both input transistors T1 and T2 are on and thus the bases of both T3 and T4 are at 0.4 V. This is insufficient to turn on the output transistor T5 and the collectors of both T3 and T4 are high which turns on transistor T6, thus pulling the output high.

A=0.2Vt 5=3.6V. T1 is on but T2 is off. With T1 on then the voltage at the base of T3 is 0.4 V and so this is insufficient to turn on both T3 and T5. However, since T2 is off then the base of T4 can rise so as to turn on T4 and then T5. The output is thus low.

A = 3.6 V, B=0.2 V. This time T2 is on and T1 off and the transistors T3 and T5 are on, forcing the output low.

A = 3.6Vt 5=3.6 V. Both T1 and T2 are turned off and so both T3 and T4 are on which therefore turns on T5 and the output is low.

Since the output is only high when both inputs are low then the circuit functions as a two-input NOR gate.

TAG:   The Totem-Pole Output Stage

Contact Us

Get answers from a reliable PCBA partner in as little as 12 hours.

NOD Electronics - PCBA - PCBA Assembly Services

Address: Block 3, #20-8 Huanxi West Rd, Tianhe, Guangzhou 510660, China

Mobile: +86-1862-0101-507


Tel: +86-020-82515913