• CMOS Logic Gates

    We have seen how to implement the logic gates NAND and NOR using NMOS technology. In CMOS the process is just the same except that the complementary PMOS transistors are added....

    2017-12-05 19:24:09 viya 112

  • CMOS Inverter Delay

    The delay for a CMOS inverter depends upon the rate of charge or discharge of all capacitors at the output. This load capacitance is due to two components called the inherent capacitance and the external load capacitance....

    2017-12-05 19:18:53 viya 121

  • CMOS Inverter Power Dissipation

    You should notice that when the input is steady at either a high or a low voltage (static condition) then one transistor is always off between Vdd and Vss. Hence the current flowing is extremely small - equal to the leakage current of the off transistor which is typically 100 nA....

    2017-12-02 16:14:38 viya 116

  • What is CMOS Inverter?

    A CMOS inverter is shown in Fig. 9.11. It consists of one NMOS and one PMOS transistor. The PMOS device is indicated by the negation sign (i.e. a bubble) on its gate and has a negative threshold voltage of typically -1V....

    2017-12-02 16:12:55 viya 116

  • The MOSFET as a Switch

    The Metal Oxide Semiconductor Field Effect Transistor (or MOSFET) has proved over the past 15 years to be a very attractive alternative to the BJT. In recent years the MOSFET has become the preferred technology mainly because manufacturing improvements have advanced further with FET processes compared to bipolar processes....

    2017-12-02 16:08:44 viya 134

  • Low-Power Schottky - 74LS Series

    The low-power Schottky clamped TTL logic family (74LS series) was released i〇 1975. This, as the name suggests, has a lower power dissipation than the 74S series. A circuit diagram for a two-input NAN...

    2017-12-01 18:24:04 viya 147

  • Schottky Clamped TTL - 74S Series

    The standard TTL series has a typical propagation delay of 10ns (the term propagation delay was introduced in Chapter 4 and will be covered in more detail later hauler) By this we mean that when an input change occurs it takes 10 ns for effect to propagate to the output. In the early 1970s it was found that this for this propagation delay could be decreased by replacing those transistors that saturate clamped transistors....

    2017-12-01 18:20:13 viya 150

  • The Totem-Pole Output Stage

    At the output of all gates there is a capacitive load (CL) caused by the input capacitance of the next stage. This could be a printed circuit board interconnect or quite simply an oscilloscope lead....

    2017-12-01 18:16:00 viya 166

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