CMOS Inverter Delay

2017-12-05 19:18:53 viya 105

The delay for a CMOS inverter depends upon the rate of charge or discharge of all capacitors at the output. This load capacitance is due to two components called the inherent capacitance and the external load capacitance. The inherent capacitance is due to the drain regions of each transistor and the wiring connecting these two drains together. The external capacitance is due either to the input capacitance of the next stage or any parasitic off-chip capacitance. The propagation delay (Tp) of a CMOS inverter, and for that matter all CMOS gates, is approximately equal to

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Example 9.11

A CMOS inverter has a total inherent drain capacitance at the output of 1pF before any external load is added. What is the propagation delay for this inverter unloaded? Also, plot a graph of inverter propagation delay versus external load capacitance. Assume that KN = KP = 64μA V-2.

Solution

Before any load is added (i.e. with 1 pF inherent capacitance) the inherent propagation delay of this inverter can be calculated from Equation 9.4. Now, since KN~ KP then the high-to-low delay will equal the low-to-high delay and it does not matter which of the two we use. Hence

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As external load capacitance is added the propagation delay will increase linearly at a rate of 6.25ns/pF. A graph of propagation delay versus external load capacitance can be plotted and is shown in Fig. 9.12. The graph does not pass through the zero delay point since the intercept on the y-axis is the inherent delay before external load is added. If we wish to decrease the delay of a CMOS gate then we must do one of two things. Either decrease the capacitance or increase K. The capacitance is decreased by reducing the size of the devices but this is limited to the minimum Unewidth6 achievable with the process. Hence if the designer is already at the limit of the process then all that remains is to increase K which is implemented by increasing the W\L ratio.

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Note: It is also possible with some CMOS processes to reduce delays by either increasing Vdd (you should check the data sheet before doing this!) or by reducing the temperature (this results in an increase in mobility and hence an increase in K).



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