In current products, most of the process and product improvements should be concentrated on specific high-defects problems. A Pareto chart should be made of the top ten problems, and projects such as DoE or process DFMA initiated to rectify these problems. In many cases, good results can be quickly achieved using these tools, especially if they focus on a particular problem that requires more specialized operating conditions than the rest of production.An example of a focused problem that can be resolved by a quality improvement project is a PCB assembly produced with special requirements. Such a case is outlined in Table 8.1 and Figures 8.2 and 8.3. This case study involves PCBs that are double-sided with mixed technology of through-hole and SMT components. The PCBs were wave soldered, resulting in poor quality. A cause-and-effect analysis shown in Figure 8.2 was performed on the problem and it was concluded that SOT-23 SMT bottom side components were the most likely reason for the defects because they resulted in a shadowing effect on the rest of the PCB components. It was decided to perform a DoE on the solder operation for this particular PCB to see if it required a different operational setup of the solder wave machine than the rest of the PCB population.
Four factors were selected (preheat, belt speed, wave height, and pot temperature), and an orthogonal array L9 with three levels was chosen for the DoE. The quality characteristic selected was smaller is better defects. Five production PCBs with SOT-23 were used for each
experiment in order to generate enough defect opportunities to allow statistical analysis of the defects- The design of the experiments and the analysis of data are shown in Table 8.1.
The factors selected for this DoE proved very easy to manipulate. The second level for each factor was the current soldering process operational settings. Preheat temperature could be set automatically using the machine setting. Special wax temperature indicators that would melt at the specified temperature were placed on the PCBs to indicate the proper preheat levels just before reaching the soldering wave. The belt speed in feet per minute was adjusted by using a potentiometer setting in the machine. The solder pot recirculating pump was adjusted with a potentiometer setting of 4, 5, or 6 to control the solder wave height. The solder pot temperature was varied in increments of 25°F. Because of the thermal mass of the solder pot, this operation took a long time, and the experiment lines sharing the same solder pot temperature were run in sequence. For example, when the solder pot temperature was set at 400oF，experiments 1，2, and 3 were run sequentially, although DoE practitioners recommend a random order when running the experiments. In addition, the choice of levels for this experiment has to be within the operating range of the process. If the solder pot temperature is too high and the conveyor speed is set too slow, the components could sustain thermal damage.
The graphical analysis in Figure 8.3 shows the relative importance of the factors and levels that were selected. The ANOVA analysis at the bottom of Table 8.1 shows the distribution of factor effects, with factor Ay the preheat temperature as being the least significant, and therefore used as the error source for the F ratio analysis. A more indepth statistical analysis could collect the errors according to each PCB, and then calculate the error variance based on the repetitions of the experiment.
The expected value (EV), which is -3.7; is much lower than the lowest defect average obtained in experiment line 7, which was 0.6 per PCB. During the conduct of the experiment, it was very difficult to convince the production operators not to forgo the mathematical analysis and immediately switch to the levels used in experiment line 7. As can be seen from the recommended levels, none of them matched the current process. The negative value of the EV is obviously within the confidence limits, since there is no such concept as negative defects. Theσerror can be quickly calculated from the square root of the variance error or mean square of the error. This is not available in this experiment as it should be derived from the replication errors, not from the assuming that the factor with the smallest SSF is the error. It is obvious that this experiment could be successful in achieving zero defects by using the graphical analysis only. The production process was changed for this one PCB to the levels recommended, and it resulted in near zero defects in the short term. For the medium term (up to 6 months after the process change) a histogram should be kept of the process before and after the DoE. In the process outlined in Figure 8.1, the histogram of the solder process defects for 6 months before and after the implementation of the DoE is shown in Figure 8.4. It can readily be seen that the average and standard deviation of the defect distribution has shifted dramatically to left, with much lower defect rates. The zero defects obtained from the DoE were not sustained over time because of the variability of the materials and new operators. The end average defect rate was 100 PPM (fourσquality), with a maximum rate of 300 PPM.