In many cases, it is not possible to obtain Cpk analysis of the electron- ic1 design because of the functionality of the circuit or module, or the need to have complete certainty in the output of the design. Some of these cases are as follows:
• Designs that perform emergency actions such as shutdowns, switching to alternate power, or sensing alarm conditions. These designs could have a desired very high Cpk value or have a sequential control scheme where one function cannot proceed until another has been positively completed.
• Synchronized digital electronic designs, where electronic signals are propagating in the circuit according to clocked conditions. Normally, the variability in the circuit performance is due to the turn on or off times of electronic gates. If not properly designed, the circuit could exhibit “race” conditions, where spurious signals are being generated in the circuit. However, the designer can use a variety of techniques to eliminate this condition, such as the use of a very fast clock to enable gate transitions or changing the phase of the signal to ensure that other derived signals in the circuit do not interfere with the original signal.
• Software designs or modules that perform specific functions. Since the software is translated into hardware-based machine instructions, and is normally duplicated every time it is run, it is difficult to quantify any variation of design. Software defects, which are measured in defects per lines of code, result from coding errors, not from the variability of the software compilers or hardware instructions.
• Mechanical or electrical designs in which the functional continuity is interrupted with adjustments or limit stops. In these cases, the tolerance analysis or stackup is not allowed to accumulate. In mechanical designs, this is referred to as breaking the tolerance loop. Although these designs remove the necessity for tight tolerances, they are much costlier to produce because of operator adjustments and additional test equipment. The policy of using adjustments in design should be addressed in the DFM or ESI phase of the design.
In these above conditions, the design six sigma quality analysis should be performed at the higher level of the design，such as the module or systems design and architecture. The interface schemes between these design elements and the product design can be evaluated through the design quality techniques mentioned in this chapter.