The Three Boolean Operators Example

The Three Boolean Operators Example

Publish Date:2017-11-01 18:13:55 Clicks: 272

The basic gates (i.e. circuit elements) available in digital electronics perform the three Boolean algebraic operations of NOT, AND and OR. The symbols for these gates are shown in Fig. J, 1. In order to both design and analyse circuits it is necessary to know the output of these gates for any given inputs.

Three Boolean Operators

Fig. 1.1 The three basic Boolean operators


The NOT operator

Since any Boolean variable can only be either 0 or 1 (Boolean algebra is a two- state system) then if it is 0 its complement is 1 and vice versa. The NOT gale performs this operation (of producing the complement of a variable) on a logic signal, so if A is input to the NOT gate then the output is represented by Y^A. Therefore if >4=0 then y=orelse^4 = I and 7=0 (there are only two possibilities).

The truth table of a logic system (e.g. digital electronic circuit) describes the output(s) of the system for given input(s). The input(s) and output(s) are used to label the columns of a truth table, with the rows representing all possible inputs to the circuit and the corresponding outputs. For the NOT gate there is only input (hence one input column, A)t which can only have two possible values (〇 and 1), so there are only two rows.3 As there is only one output, Y, there is only one output column. The truth table for the NOT gate in Table 1.2 shows that 1 if d = 0, and y=0 if d So the complement of The NOT gate is also sometimes referred to as an inverter due to the fact that it complements (inverts) its input.

The number of possible inputs, and hence rows,is given by where/is the number of inputs) since each of the (inputs can only take one of two possible values (0 and I).

Three Boolean Operators


The AND operator

The AND operator takes a number of variables as its input and produces one output whose value is 1 if and only if all of the inputs are 1. That is the output is I if input 1 and input 2 and ail the other inputs are 1. Hence its name.

Considering a two-input (although it can be any number) AND gate its truth table will have two input columns, A and B, and one output column, Y. With two inputs there are 22=4 input combinations (since both A and Scan be either 0 or 1) and so four rows. The output of the gate, Yy will be 0 unless all (i.e. both A and B) inputs are 1, so only the last row when A and B are 1 gives an output of 1. The truth table (see Table 1.2) describes completely the output from an AND gate for any combination of inputs.

Alternative, but exactly equivalent, descriptions of this operation are given by use of either the circuit symbol or the Boolean equation, Y=A • B. (This is true of all combinational logic circuits.)

Example 13                        

Consider a three-input AND gate. How many columns and rows would its truth table have? What would the Boolean expression describing its operation be? What would its truth table and circuit symbol be?


The truth table would have four columns; three for the inputs and one for the output. Since there are three inputs it would have 2'=8 rows corresponding to all possible input combinations. Its Boolean algebraic expression would be Y=A B Cy assuming the inputs are B and C. Its truth table and circuit symbol are shown in Fig. 1.2.

Three Boolean Operators

The OR operator

The OR operator takes a number of variables as its input and produces an output of 1 if any of the inputs are 1. That is the output is 1 if input 1 or input 2 or any input is !. The layout of the truth table for a two-input OR gate is the same as that for the two-input AND gate for the same reasons given above (since both have two inputs and one output). The entries in the output column are all that differ with Y= 1 whenever any input, either A or B, is 1.4 Note that this includes an output of 1 if both inputs are 1.5 The Boolean algebraic equation for this gate is Y—A+B.

Example 1.4    

Draw the circuit symbol and truth table for a four-input OR gate.


These are shown in Fig. 1.3.

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