The Introduction of Flip-flops
Flip-flops' are vital ingredients in all except purely combinational logic circuits and are therefore extremely important. The SR (Set-Reset) flip-flop was introduced in the last chapter and illustrates an important point, namely that all flip, flops are asynchronous sequential logic circuits. However, by controlling their use they can be considered as synchronous circuit elements, which is exactly the approach taken here. Rather than providing a detailed description of how flip, flops are designed and operate，they are presented as discrete circuit dements (e.g. like a multiplexer or full adder) to be used in subsequent designs.
In general, flip-flops possess data inputs (e.g. the S and R inputs), an output, Q (and its complement, Q), and also (as we will see) a ‘clock’ input which controls the activation, or clocking, of the flip-flop. That is the timing of the change in the flip-flop’s output in response to its inputs.
The SR flip-flop can be set, or reset, or held in the same state via control of its inputs, However, it cannot be made to change state (i.e. its output give the complementary value) or toggle. Further thought reveals that if it could its operation would be unpredictable since it is an asynchronous circuit and therefore if made to toggled would do so continuously (i.e. oscillate) until new inputs were presented.
However, by gatting the inputs to an SR flip-flop via AND gates under control the flip-flop's complementary outputs (Q and Q) it is possible to produce a flip-flop whose output can be made to toggle (i.e. go from 0 to 1 or vice versa) when activated (see Problem 6.1). This is then an example of a T-type (Toggle) flip-flop output either remains the same (when the input T^O) or toggles (when T= 1)-
Alternative input gating (again using AND gates via control of the flip-flops outputs) allows the SR flip-flop to be transformed into a device called a JK. flop which combines the characteristics of the both the SR and T-types Problem 6.2). The JK operates as for an SR flip-flop with the addition that its inputs can be 1, in which case the output toggles.
The fourth and final type of flip-flop has the simplest operation acting only to delay the transfer of its input to its output. Clearly the activation of this D-type(Delay) flip-flop must be controlled externally since otherwise it would simply be a wire link. Hence it has three external connections: the input, D, and output, Q, and a clock input which controls the timing of the transfer of the input value to the output.
In fact all types of flip-flops are available in clocked form which basically means that they have an additional clock input, with the flip-flop’s outputs only responding to the input conditions when the clock line goes active (i.e. the flip-flop is ‘clocked’).
To summarise, there are four types of flip-flop:
SR Set-Reset; must not allow both inputs to be 1 simultaneously.
T Toggle type; on clocking the output either remains the same or toggles depending if the input is 0 or 1.
JK Offering the capabilities of both the SR and T types.
D Delay-type flip-flop; upon clocking the output follows the input.
The operation of these four flip-flops can be described in several ways.
• A truth table which shows what the flip-flop's output, will be for all possible input combinations. (Note the use of Q and Q in the output column which respectively mean that the output either remains as it is or toggles.)
• An excitation table which gives the inputs that must be used to produce a given output transition.
* A Karnaugh map containing the same information as the truth table but in a different format. (Note there is a cell for every possible value of Q and so more cells than rows in the truth table.)
* The next state equation which is the minimised form of the output, Q+, from the Karnaugh map as a function of the flip-flop*s inputs and the flip-flop s present output (state), Q.
These are shown for all types of flip-flop in Table 6.1.
6.1.2 Flip-flop operation
Being asynchronous circuits the brief description of flip-flops given above dearly cannot adequately describe their precise operation.2 Although the SR flip-flop does find uses in its basic (unclocked) form (see Section 6.2.l), the other three types are always clocked, that is the changes in the outputs occur under the control of a clock3 signal.
Given that a flip-flop is clocked there are still several ways in which this can be performed. For instance the clock (or control) line going active may then that any changes in the inputs (during the active clock signal) take effect at outputs. In this case the flip-flop is said to be transparent (since as long 3s ^ clock is active the outputs can ‘see’ right through to the inputs).
With such a clock signal the flip-flop is effectively a level triggered device with the inputs taking effect as soon as the clock line reaches, and whilst it remains at, its active level. Obviously in order for such devices to operate correctly it will usually be necessary to ensure the inputs do not change when the clock is active.
Alternatively flip-flops may be edge triggered. An edge refers to a rising or falling logic signal (e.g. going from 0 to 1 or 1 to 0), referred to as positive and negative edges respectively. An edge-triggered flip-flop will change its outputs in response to the inputs when an edge appears on the clock; line. Therefore it is not transparent since ideally it responds to the inputs at a particular instant in time. This is the most common form of flip-flop used and the one that we will use in subsequent designs.