Implementation of The Steering Logic

Since for this type of counter in general we need the input to the nth T-type used to construct the circuit to be TN=Q0 *Q2*…QN-1, = TN-1* QN-1 it is clear there are two ways in which the steering logic can be generated. One approach is to actually AND together all of the previous outputs, which for a counter with n flip-flops requires AND gates with from 2 up to (n-1) inputs. The advantage of this implementation is the only delay introduced is that of the single AND gate with the disadvantage that an AND gate with a prohibitively large number of inputs may be required2 and the outputs from the flip-flops may also have to prohibitively large number of inputs.

The alternative, serial approach, is to use only two-input AND gates and at each stage AND together the output from the each flip-flop with its input (i.e. its steering logic), for example T3=T2*Q2. The disadvantage here is that this introduces a delay because the output of the steering logic is using a signal that must propagate (ripple) through all of the AND gates.