The design of asynchronous sequential circuits follows essentially the reverse of the analysis procedure. That is from flow table, to transition table, to Karnaugh maps for the individual output variables and finally the Boolean equations. However, in order to produce reliable circuits the procedure becomes somewhat more complex than this simplified description suggests.
Consequently, what follows is a discussion of the design process, rather than its application which can be found in other texts.
The design route
Asynchronous circuit design usually begins with the primitive flow table which is similar to the flow table but only possesses one stable state per row. This is then studied to see whether any of the resulting states are equivalent (in terms of their stable states, where their unstable states lead and the associated outputs). If any states are equivalent then they can be combined to produce the minimm-row primitive flow table (still with one stable state per row) which can be further reduced by merging equivalent rows to give the flow table we have used during circuit analysis.
The state assignment is then performed in which binary codes are given to the states in the flow table. Note that there are many state assignments possible (i.e. any binary code can be given to any state). This leads to the transition table and then on to the final Boolean equations for the output variables.
Unfortunately the process is not quite this straightforward, and further thought is necessary to produce a reliable circuit. We saw in Section 4.3 that combinational circuits can contain hazards and therefore the effects of these in the combinational block of our asynchronous circuit must be taken into account. In addition asynchronous circuits possess their own potential hazards.
We have seen how relaxation of fundamental mode operation can lead to race conditions. In a similar way if circuit possesses more than two internal variables and these change 'simultaneously' then the order in which they change may result in different eventual states being reached. (In this situation the flow table will have more than two rows, and the order in which these rows are visited within the same column, upon external inputs being changed may differ and lead to an unexpected stable state.) Techniques for predicting and eliminating such problems exist and this is done during state assignment. It may involve the introduction of additional intermediate states which are visited transiently during the actual Spikes in the outputs may occur due to the same cause (i.e, transiently visited required transition.
Spikes in the outputs may occur due to the same cause (i.e. transiently visited states)and can be eliminated by consideration of the 'don't care' conditions when drawing up the output table.
Finally, even if neither critical races nor hazards in the combinational logic block exist an asynchronous circuit may still possess essential hazards. These are due to internal delays in the circuit which make it appear as if a single external input has changed three times. (i.e. 0→1→0→1) rather than just once. These can be eliminated by adding in appropriate delays to the circuit to ensure signals prop- agate in the 'correct' order.
In principle asynchronous design is straightforward but the presence of hazards means that care must be taken for such designs to function correctly. The hazards are usually dealt with by: firstly eliminating critical races; then ensuring all combinational logic is free of hazards; and finally spotting and eliminating essential hazards by the addition of strategically placed delays.