The ‘memory’ of previous outputs in an asynchronous sequential circuit is provided by direct feedback from the internal output(s), Y, to the internal input(s), y, of the combinational logic block. The essence of under- standing asynchronous circuits is to realise that for the circuit to be stable the outputs generated by the input(s) must be equal (i.e. Y=y), since these two sets of signals are connected via the feedback.
If this is not so then the circuit will be unstable with the output(s) (unmatched to the input(s) acting as different input(s) and so producing new output(s) which will then be fed back again. This process will repeat until a stable condition is reached. This concept will become clearer as we analyse actual asynchronous sequential circuits.
The first stage of asynchronous sequential circuit analysis is to 'break' the feedback paths and treat the output(s) being fed back and the corresponding input(s), linked via the feedback, as separate variables. The circuit will only be stable when these signals have the same values.
The conditions for which the circuit is stable are known as the 'stable states' (Note that for asynchronous sequential circuits these total stable states depend upon all of the inputs, i.e. both internal and external ones, and not just the values of the feedback, i.e. the present state, variables). Circuit analysis involves finding out how these stable states are both reached and related to one another, whilst design involves producing a circuit which enters the required stable states for the desired input patterns.