Common Combinational Logic Circuits

# Common Combinational Logic Circuits

Publish Date:2017-11-07 16:29:05 Clicks: 169

There are a number of combinational logic circuits which are used so frequently that they are often considered to exist as circuit elements (like logic gates) in their own right. Note that the forms of these circuits given here are those that implement the basic functions. When provided as 'building blocks’ for digital design some of these may have additional combinational logic circuits attached to their inputs that allow extra control of their action.

4.1.1  Multiplexers

Multiplexers provide a way of selecting one out of many digital signals. A multiplexer will in general have n inputs, and obviously one output, with m control lines which are used to select one of the n inputs. The block diagram of a multiplexer (mux) is shown in Fig. 4. 1.

Which of the n-input channels is routed through to the output is determined by the bit pattern on the m control lines. Hence, n, the number of input lines that can be multiplexed is 2m. The basic structure of an n-input multiplexer is input AND gates (that is one AND gate to decode each of the n=2m possible combinations of the m control inputs), all feeding into a single OR gate. The extra (to the m control lines) input to each gate is connected to one of the n inputs. Multiplexers are usually referred to as n-to-1 or 1-of-n multiplexers or data selectors.

The operation is based upon the fact that only one of the 2m possible input combinations can ever be applied to the control inputs at any one time, and therefore only the corresponding and gate will be capable of giving an output other than 0. This is the gate whose input will be routed through to the output. Multiplexer

Figure 4.2 is the circuit diagram of a 2-to-l multiplexer. Note that it has two inputs (n=2), with a single control line (m= 1). If A=0 then the output from the AND gate with Z), as an input must be 0 (since anything AND'd with 0 is 0, Equation 1.6) whilst the output from the other AND gate will be A*D0=1*D0=D0*So, the output from the multiplexer is r=D0+0=D0 (Equation 1.8). By similar reasoning if ^ = 1 then K=Z),.In Boolean algebraic terms:

Y=A-DQ+A-Dl

One way of thinking of the action of a multiplexer is that only one of the AND gates is ever activated and so allows the input signal fed to it through to the OR gate. This is illustrated in Fig. 4.3 which shows one of the AND gates from an 8- to-1 multiplexer which therefore has three control signals A, B and C. The gate shown controls the passage of input D3 which will be selected for an input of ABC. The output from this gate is ((ABC) - D3),which will be D3 when the product term ABC=1, and 0 otherwise. Hence the presence of this product term effectively 'activates’ the gate, meaning the output is then D3*Any other input combination. means the output from the gate is always 0. Only one ANDgate in a multiplexer is activated at a time and it is therefore its output that appears as Y, the output the OR gate and hence the multiplexer.

Draw the circuit diagram and truth table, and give the Boolean describing the output, of a 4-to-l multiplexer. 