Specification for the Four-Bit Binary Adder

Specification for the Four-Bit Binary Adder

Publish Date:2017-11-10 18:15:06 Clicks: 129

A four-bit binary adder is required to add together two four-bit binary numbers plus one carry-in bit, and produce a four-bit sum plus a carry-out bit. This is shown diagramatically in Fig. 4.14.

Four-Bit Binary Adder


By definition this is a combinational logic problem as no memory is involved, and the outputs (the sum and carry-out) depend solely upon the inputs. The truth table for this circuit will have nine input columns, and hence 29 = 512 rows, and five output columns. We will now look at four different ways this four-bit adder could be constructed. The first two consider the use of fundamental and then minimised two-level circuits; the second two are developed by taking a closer look at the mechanics of the addition process.

Two-level circuit Implementation

Fundamental form

We begin to consider the feasibility of constructing the four-bit adder in fundamental two-level form by looking at the output from the first sum bit, S0. Since the result of the addition will be equally odd and even then the output column for will contain 256 1’s and 256 0’s. Since the truth table has nine inputs, and we need to use all of these as we are considering a fundamental sum of products implementation,then our two-level circuit will need 256 nine-input AND gates plus a 256-input OR gate to perform the summing. This is clearly impractical so we immediately rule out this method.


Minimised form

The most complex Boolean function in the circuit is the one for Cout since it depends on ail of the nine inputs. The minimised expression for Cout contains over 30 essential prime implicants, which means that this many AND gates plus an OR gate with this number of inputs would be needed for a minimised two-level implementation. Furthermore, some of the input variables (or their complements) must be fed to up to 15 of the 31 essential prime implicants.

Clearly the large number of gates required, the large number of inputs they must possess, and the fact that some signals must feed into many gates, means that this implementation is also impractical, although it is an improvement on the fundamental two-level form. So although the two-level implementation is theoretically the fastest (assuming ideal gates) we see that for this application it is not really practical.

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