What is Moore Model Circuit?
Now we shall design a D-type based circuit that will count up or down, under the control of a single external input, through the first five prime numbers (in binary). We must ensure that the circuit will return to state (binary count o〇 1 if an unused state is entered.
Taking 1 as a prime number the first five primes are 1, 2, 3, 5 and 7. Therefore three flip-flops arc required. States (i.e. binary counts) 0,4 and 6 are unused and must lead to state 1 (i.e. 0012).
Fig. 8.3 shows: the state diagram; the necessary next states in terms of the present states and external input control, X; together with the Karnaugh maps for the next states, Q\ of the three flip-flops in terms of the present states and X. By minimising the Karnaugh maps we determine that we need:
These give the Boolean expressions that must be implemented using combinational logic and used as the inputs to the three D-type flip-flops.
In this design the ‘count’ state can be taken straight from the flip-flops' outputs. Alternatively a particular state could be decoded using appropriate combinational logic. In both cases these would fit the Moore model since the outputs E would be independent of the external input, X.
A further option would be to additionally use the input X to decode the arrival into a particular count direction. This would give a circuit that would conform to the Mealy model. With such circuits care must be taken because changes in the external inputs may not be synchronised to the clock, in which case neither will changes to the external outputs. This may lead to transient states (and so spikes) in the outputs.