CMOS Inverter Power Dissipation

You should notice that when the input is steady at either a high or a low voltage (static condition) then one transistor is always off between Vdd and Vss. Hence the current flowing is extremely small - equal to the leakage current of the off transistor which is typically 100 nA. As a result of this the static power dissipation is extremely low and it is this reason that has made CMOS such a popular choice of technology.

For input voltages between VT and Kdd- VT then the individual MOS transistors will be switched on by an amount dictated by Equations 9.1 and 9.2 and thus current will flow from Vdd to Vss. When the input voltage is Vdd/2 both transistors will be turned on by the same amount and hence the current will rise to a maximum and power will be dissipated. On many integrated circuits, several thousand gates exist and hence this power dissipation can be large. It is for this reason that the input voltage to a CMOS circuit must not be held at Vdd/2. When the inputs are switching the power dissipated is called dynamic power dissipation. However, as long as the input signals have a fast rise and fall time then this form of dynamic power dissipation is small. The main cause of dynamic power dissipation, however, in a CMOS circuit is due to the charge and discharge of capacitance at each gate output. The dynamic power dissipation of a CMOS gate is therefore dependent upon the number of times a capacitor is charged and discharged. Hence as the frequency of switching increases so the dynamic power dissipation increases. The dynamic power dissipation for a CMOS gate is equal to

Where f is the switching frequency and CL is the load capacitance.

The total power dissipated in a CMOS inverter is thus the sum of the static and dynamic components.

Example 9-9                                

Compare the power dissipated by a CMOS inverter driving a 50 pF load at (a) 10kHz and (b) 10 MHz. What average current flows in each case. Assume a 5V power supply.

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