A CMOS inverter is shown in Fig. 9.11. It consists of one NMOS and one PMOS transistor. The PMOS device is indicated by the negation sign (i.e. a bubble) on its gate and has a negative threshold voltage of typically -1V. To turn on a PMOS device we require a voltage, VGS, more negative than -1 V. Notice that the two drains of the two MOS transistors are connected together and form the output whilst the two gates form the single input. Due to the difference in the mobilities of the two devices the PMOS device is made with its W/L ratio 2-3 times larger than the NMOS device. This results in the two transistors having the same value of K so that both will have the same electrical performance.
The circuit operation depends upon the individual gate-source voltages. Whei the input voltage is 5 V then the NMOS VGS is 5 V and hence this device is However, the PMOS VGS is 0 V and so this device 15 turned off. The output voltage is thus pulled down to OV. Now with the input at 0 V the NMOS VGS is 0 V and hence is turned off. However, the PMOS VGs is -5V and is thus turned 〇 (remember a voltage more negative than the threshold voltage is needed to turn on a PMOS device). With the PMOS device on, the output voltage is pulled up t V^. The circuit thus operates as an inverter or a NOT gate.