We have seen how to implement the logic gates NAND and NOR using NMOS technology. In CMOS the process is just the same except that the complementary PMOS transistors are added.
What function is implemented by the circuits shown in Fig. 9.13(a) and (b)? Although not shown you should assume that the gate inputs labelled A are connected together (similarly for gate input B).
Fig. 9.13 (a): with either A or B or both high then at least one NMOS transistor is on and the output is pulled down to ground. As far as the PMOS transistors are concerned if an input is low then that PMOS transistor is turned on. Now, in this case the PMOS transistors are in series and hence only when both inputs are low will the output be pulled high. The circuit of Fig. 9.13(a) is thus a NOR gate.
Fig. 9.13(b): this time the PMOS transistors are in parallel and hence we only need one input to be low for the output to go high. Conversely, the NMOS transistors are in series and the only way for the output to go low is for both inputs to be high. The circuit of Fig. 9.13(b) is thus a NAND gate.
Note: as for the CMOS inverter when the inputs are held static at either logic 1 or logic 0 then one transistor is always off between and the current flow is just due to the leakage current of the off transistor. The static power dissipation is therefore again extremely low.