As we have seen in earlier chapters we can implement many complex combinational functions by connecting together the basic gates NAND and NOR- However, the result is not an efficient use of transistors. If we introduce some basic rules we can produce a more efficient CMOS transistor implementation consider for example Fig. 9.14(a) which shows a CMOS circuit which implements the function:
The basic rules are as follows:
1. Concentrate on the NMOS network and note that from the function ‘f’ we can see that terms OR’d are represented as transistors in parallel and those AND'd are transistors in series, i.e. A is in parallel with B and C is in parallel with D, whilst these two networks are in series with each other.
2. To produce the PMOS network we just replace series networks with parallel networks and parallel with series.7
Notice that the number of transistors needed for this function is eight. If we try to implement this function directly with a NAND/NOT/NOR gate approach the circuit shown in Fig. 9.14(b) would be needed and the number of transistors required would be 16 - a rather wasteful use of silicon.