The programming of field programmable logic devices is implemented directly via a computer. The software needed for PALs and PLAs is usually a simple matter of producing a programming file called a fuse or an EPROM bit file. This file has a standard format (called JEDEC) and contains a list of 1's and 0's. This file is automatically generated from either Boolean equations, truth tables or state diagrams using programs such as ABEL (DataIO Corp.), PALASM (AMD Inc.) and CUPL (Logical Devices Inc.). In other words the minimisation is done for you and it is not necessary to draw out any Karnaugh maps. Software programs that can directly convert a schematic representation into a JEDEC file are also available. Since these devices have only an MSI complexity level then the software tools are relatively simple to use and also inexpensive.
The FPGAs, on the other hand, have capacities of LSI and VLSI level and are much more complex. Since FPGAs are similar in nature to mask programmable gate arrays the associated CAD tools have been derived from mask programmable ASICs and follow that of Fig. that is: schematic capture (or VHDL), prelayout simulation, layout, back annotation and postlayout simulation.
It should be noted that FPGA simulation philosophy is somewhat different from mask programmable gate arrays. With mask programmable devices, 100% simulation is absolutely essential since these circuits cannot be rectified after fabrication without incurring large financial and time penalties. These penalties are virtually eliminated with FPGA technology due to the fast programming time in the laboratory and the low cost of devices. For one-time programmable devices (such as Actel) the penalty is the price of one chip whilst for erasable devices (such as Xilinx) the devices can simply be reprogrammed. Hence the pressure to simulate 100% is not as great.
For those devices that are reprogrammable this results in an inexpensive iterative procedure whereby a device is programmed and then tested in the final system. If the device fails it can be reprogram with the fault corrected. For OTP type FPGAs then a new device will have to be blown at each iteration; although it will incur a small charge the cost is considerably less than mask programmable arrays. It is not uncommon for FPGA designs (both reprogrammable and OTP) to experience four iterations before a working device is obtained. This is totally unthinkable for mask programmable designs where 'right first time approach' has to be employed-hence the reliance on the simulator.
Since fuses, SRAM/MUX cells, etc., are used to control the connectivity the delays caused by these elements must be added to the wire delays for postlayout simulation. Hence it is for this reason that FPGAs operate at a lower frequency than mask programmable gate arrays. The large delays in the routing path also mean that timing characteristics are routing dependent. Hence, changing the placement positions of core cells(by altering the pin out for example)will result in a different timing performance.It should also be noted that the prelayout simulation of FPGAs on some occasions is only a unit delay (i.e. 1 ns for all gates) or functional simulation. It does not take into account fan-out individual gate delays, set-up and hold time, minimum clock pulse widths (i.e. spike and glitch detector), etc., and does not make any estimate of the wire delay. Hence the simuaon at this stage is not reflective of how the final design will perform. To obtain the true delays the FPGA must be laid out and the delays back annotated for a postlayout simulation. This will provide an accurate simulation and hence reveal any design errors. Unfortunately, if a mistake is found then the designer must return all the way back to the original schematic. The design must again be prelayout simulated,laid out and delays back annotated before the postlayout simulation can be repeated. This tedious iterative procedure is another reason why FPGAs are usually programmed prematurely with a limited simulation. It should be mentioned that an FPGA is sometimes used as a prototyping route prior to migrating to a mask programmable ASIC. Hence the practice of postlayout simulation using back annotated delays is an important discipline for an engineer to learn in preparation for moving to mask programmable ASICs.
When all the CAD stages are completed the FPGA net-list file is converted into a programming file to program the device. This is either a standard EPROM bit file for the Xilinx and Altera arrays or a fuse file for the Actel devices. Once a device is programmed, debug and diagnostic facilities are available. These allow the logic state of any node in the circuit to be investigated after a series of signals has been passed to the chip via the PC serial or parallel port. This feature is unique to FPGAs since each node is addressable unlike mask programmable devices. FPGA CAD tools are usually divided into two parts. The first is the prelayout stage or front-end software, i.e. schematic and prelayout simulation. The CAD tools here are generic (suitable for any FPGA) and are provided by proprietary packages such as Mentor Graphics, Cadence, Viewlogic, Orcad, etc. However,to access the FPGAs the corresponding libraries are required for schematic symbols and models.
The second part is called the back-end software incorporating: layout; back annotation of routing delays; programming file generation and debug. The software for this part is usually tied to a particular type of FPGA and is supplied by the FPGA manufacturer.
For example consider typical CAD route with Actel on a PC. The prelayout (or front end) tools supplied by Viewlogic can be used to draw the schematic using a package called Viewdraw and the prelayout functional simulation is performed with Viewsim. In both cases library files are needed for the desired FPGA. Once the design is correct it can be converted into an Actel net-list using a net-list trans lator. This new file is then passed into the CAD tools supplied by Actel (called Actel Logic System-ALS) ready for place and routing. The parasitic delays can be extracted and back annotated out of ALS back into Viewlogic so that a post layout simulation can be performed again with Viewsim. If the simulation is not correct then the circuit schematic must be modified and the array is placed and routed again. Actel provide static timer to check set-up and hold time and calculate the delays down all wires indicating which wire is the heaviest loaded. A useful facility is the net criticality assignment which allows nets to be tagged depending on how speed critical they are. This facility controls the placing and routing of the logic in order to minimise wiring delays wherever possible.The device is finally programmed by first creating a fuse file and then blowing the fuses via a piece of hardware called an activator This connects to an Actel programming card inside the PC. As an example of the length of time the place and route software can take to complete the authors ran a design for a 68 pin Actel 1020 device. The layout process took approximately 10 minutes using a 486, 66 MHz PC and utilised 514 (approximately 1200 gates) of the 547 modules available (i.e.a utilisation of 94%). In addition on the same computer the fuse programming via the activator took around minute to complete its program. With mask program- mable ASICs, however, the programming step can take at least four weeks to complete! This is one of the great advantages that FPGAs have over mask programmable ASICs. Note, however that as with mask programmable arrays the FPGA manufacturers only provide a limited range of array sizes. The final design thus never ever uses all of the gates available and hence silicon is wasted. Also, as the gates are used up on the array the ability for the router to access the remaining gates decreases and hence although a manufacturer may quote a maximum gate count for the array the important figure is the percentage utilisation.
Actel FPGAs also have comprehensive postprogramming test facilities available under the option 'Debug'. These consist of: the functional debug option; and the in-circuit diagnostic tool. The functional debug test involves sending test vectors from the PC to the activator, which houses the FPGA during programming, and simple tests can be carried out. The in-circuit diagnostic tool is used to check the real time operation of the device when in the final PCB. This test is 100% observable in that any node within the chip can be monitored in real time with an oscilloscope via two dedicated pins on the FPGA.
The Xilinx FPGA devices are programmed in a similar way by using two pieces of software. Again typical front-end software for these devices is Viewlogic utilising viewdraw and Viewsim for circuit entry and functional simulation respectively. The net-list for the schematic is this time converted into a Xilinx net-list and the design can now move into the Xilinx development software supplied by Xilinx (called XACT). Although individual programs exist for place and route, parasitic extract, programming file generation, etc., Xilinx provide a simple to use compilation utility called XMAKE. This runs all of these steps in one process Parasitic delays can again be back annotated to Viewsim for a timing simulation with parasitics included. A static timing analyser is again available so that the effects of delays can be observed on set-up and hold time without having to apply input stimuli. Bit stream configuration data, used in conjunction with a Xilinx provided cable, allow the data to be down-loaded to the chip for configuration. As with Actel both debug and diagnostic software exist such that the device can be tested and any node in the circuit monitored in real time. The bit stream data can be converted into either Intel(mcs-86), Motorola(EXORMAX) or Tektronix (TEKHEX)PROM file formats for subsequent PROM or EPROM programming. The one disadvantage of these devices as compared to the Actel devices is that when in final use the device needs to have an associated PROM or EPROM which increases the component count.