Standard cell

Standard cell

Publish Date:2019-09-26 17:06:31 Clicks: 226


The advantages of fast turnaround time and relatively low cost offered by gate arrays is counterbalanced by several problems. The first is that silicon is wasted because a design does not use all the available gates on the array. Also, it is not known by the manufacturer which pad on the array is to be an input or an output and so silicon is further wasted by the inclusion of both input and output circuits at every pad. As the chip price is proportional to die size then this can be uneconomical when large volumes are required. In addition, because all the transistors in a gate array are the same size then when transistors are placed in series long delays occur. This happens on the PMOS chain for NOr and the NMOS chain for NAND. Consequently the gates cannot be optimally designed and the delays τplh and τplh are asymmetrical. If the WIL's of the transistors were individually adjusted for each gate type the delays would be shorter.

The standard cell approach gets around these problems. Here, the designer again has available a library of logic gates but the design starts with a clean piece of silicon. Hence only those gates selected for a design appear on the final chip and no silicon is wasted. It is also known which pads are to be input and output thus further saving silicon. The standard cell chip is therefore smaller than the gate array. This device is also faster partly because it is smaller and the routing is shorter (hence smaller wire delays) and partly because the library of logic gates is optimally designed by the manufacturer. This is achieved by adjusting the WIL's of the transistors in each gate so as to achieve optimum delay.

Since the standard cell only uses those gates that are needed for a design then each chip is of different size and is unique. Hence all masks are required, which can be of the order of 8-16 masks where each mask costs £1000-£2000! The NRE costs are therefore considerably higher and the production times longer compared to a mask programmable gate array. This approach is therefore only economical when relatively large volumes are involved. However, reduced prototyping costs are again available by using multiproject wafers.

Libraries for standard cell (and gate arrays have become quite sophisticated Not only are the basic and complex gates provided but also counters and UARTs (serial interface) exist. Incredibly some manufacture are even offering complete processor cores such as the Z180 by VLSI Technology, TMS320C50 by TI and the 80486 by SGS Thomson.

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