The PCB manufacturing process is not standard and is heavily dependent on design parameters. A low-component-density PCB could be implemented in a two-sided (two-layer) fabricated PCB, which does not require inner-layer processing or lamination. Similarly, many fabricators use inner-layer inspection only for very dense or controlled impedance designs. The type of solder mask selected (screened, dry film, or liquid photoimageable) is dependent on the density of signal lines and the types of assembly requirements for the PCBs.
The operating cost of a manufacturing facility will include overhead for administration and marketing. However, these are usually applied evenly across all products and are therefore not design-dependent.
By examining the list of cost factors, the PCB features that affect the cost of the design can be identified. The number of layers will determine how many times the innerlayer processing rate is applied and the material cost of copper-clad dielectric and prepreg material for adhesion of the layers. Since the drill cost rate is often expressed per hole, this cost will depend on the stack height, which is in turn based on the PCB thickness, hole diameter, and the required accuracy of the location of the drilled hole. Too tight a hole tolerance, which affects the solder mask operation, will result in a lower drilled stack, and therefore higher drilling costs but less misregistration defects. Most fabricators process full panels (such as the 18 x 24 size), so the more images or PCBs that can be designed to fit on a single panel, the smaller the PCB cost.
The cost of a fabricated PCB should provide a conversion process from PCB design features to manufacturing cost An important part of this process is the designers understanding of the manufacturing process, capabilities, and constraints. For example, the dry film solder mask is the most expensive, yet offers the best quality in terms of soldering defects in PCB assembly. The inverse is true of the screened solder mask.
To calculate the effect of different design alternatives, a manufacturing engineer must provide information about each cost parameter in the fabrication process that would influence the final cost. The cost (C/) for each PCB parameter is:
Where Pi is the PCB specific number applied for each cost parameter and Ft is the respective cost factor for the fabricator.
The cost factor, Fi is derived from the fabricator cost rates based on their actual material, labor overhead, and support costs. For example, the relative cost factor Filp of inner layer processing is calculated from the following formula:
Where Cu and Clo are the inner layer imaging and etching direct labor and overhead expended from the last financial period reported, respectively，and is the department support and maintenance costs such as percentage of utilities, maintenance, and general management costs incurred to support the inner layer department. NL is the number of layers consumed by the fabricator during that period. Obviously, this cost factor system necessitates alternative accounting procedures by which costs are accumulated based on the cost factor structure.
Cost factor systems provide a standard measure of the contribution of individual design features to overall PCB manufacturing cost. They allow manufacturing engineers to compare multiple design alternatives in order to select the optimum design. Yield prediction for PCB fabrication is an important element of the coat equation, yet it has proven to be difficult to estimate. Examples given above suggest that there is a trade-off between the higher cost of materials and processes and the result ant yield from them.
Historically, PCB tooling departments provided manufacturability reviews of new PCB designs prior to production release. These re- views are successful in identifying major errors such as spacing violations or missing features. However, in most cases, the yield has already been determined by decisions made far upstream and it is too late to significantly alter the design- Although factors that contribute to yield loss are well known (including high layer county fine lines, and small holes), higher performance unavoidably requires selecting features that create less-manufacturable PCBs.
Yield prediction is required to evaluate the effect of feature selection on yield at the early stages of the design process, thereby minimizing the PCB cost for a set of performance requirements. One possibility is to express the complexity of a design technology set with a single standard metric containing values of the significant design elements. The yield prediction model then becomes a functional relationship between fabrication yield and the complexity metric. This method allows several different design alternatives to be quantitatively compared to determine the yield (or cost) improvements associated with selected design changes. An example of complexity-based process DPUs from a typical PCB fabrication shop is shown in Table 6.2.
The development of a complexity metric should be guided by a study of the influence of design elements on fabrication yield. First, each printed circuit manufacturing process should be examined to uncover possible sources of yield loss. Then the most common fatal defects observed in manufacturing are investigated to determine probable design and process-related causes. This complexity factor is based on two elements: the geometry of the PCBs as well as any special electrical requirements that can lead to material and process considerations in plating, solder coating, or solder mask selection.
The geometry of the PCBs is based on the components to be used, their pad sizes, and the line widths and spaces connecting them. Small rectangular pads for SMT components are replacing the round insertion pads of TH technology. The old standard of 0.060,( insertion component pads on 0.100w centers has been replaced with rectangular pads that are only 0.030M wide on 0.050H centers, or even 0.005f,wide pads on 0.010/, centers for TAB configurations. Added to these factors are the increasing number of interconnecting holes or vias and their associated small-diameter pads. Many SMT device component leads require an attached via pad for electrical testing as well as interconnection to inner layers, this connectivity is an important part of the complexity metric.
The most common expression of connectivity is inches of wiring per square inch of circuit board (in/in2). One method of measuring this factor is the total line lengths necessary to implement the PCB design, based on the theoretical optimum placement of the components on the PCB. In the PCB industry, the line length is measured by track (number of traces between grid points) and layer count. Unfortunately, this metric can only be known after the layout is completed, and therefore cannot be used to describe the necessary connectivity required to select an alternative.
Most designers currently make an estimate of track and signal layer count from prior experience. The CAD software autorouter is set up with “standard” feature dimensions (usually from a design specification) and allowed to work away. After the autorouting cycle is completed, the layout is checked for remaining disconnects. If a significant number of signals are still unconnected，the usual procedure is to add another pair of signal layers.
A possible design alternative is to increase track by using smaller trace widths, spacing and/or pad sizes, and thus reducing the total layer count and PCB costs. However, this increased track could be offset by the greater use of fabrication technology.
A geometry performance model should use the information available to the PCB designer prior to the start of layout phase. Several industry studies have demonstrated that wiring demand can be calculated from the number of input/output connections (I/Os) per component, the number of components, and the approximate spacing between components. This can be expressed in terms of equivalent integrated circuits (EICs). In addition, the choice of the pad, hole, and line widths and spaces should be determined prior to layout. If the capability of the CAD system and its operator can be expressed as an efficiency factor, then wiring capacity and PCB technology sets can be estimated from standard EIC densities.
The overall fabrication yield of a printed circuit board is limited by the maximum capabilities and normal process variations of the individual steps. The key processes that introduce yield loss are:
Image transfer Copper etching Lamination Drilling Metallization Solder mask
An analysis of PCBs scrapped at major fabrication shops revealed that the majority of fatal defects fell into three categories: electrical opens, electrical shorts, and solder mask defects (e.g., cracking, flaking, or loss of adhesion). A list of possible design-related causes of these defects is given in Table 6.3.
In order to verify the apparent effect of these features on yield and obtain an estimate of their relative significance, actual production yield data should be collected for current production part numbers.